Pipeline processing is a method of processing information. A pipeline consists of several units that perform tasks on information. After a first unit has completed its work on the information, the information is passed to another unit. The work done on the information by the pipeline is not completed until it has passed through all the units in the pipeline.
The advantage of pipelining is that it increases the amount of processing per unit time. This results in instructions being handled in less cycles.
In FIG. 1, an exemplary diagram of a Microprocessor 100 using pipeline processing is shown. The Microprocessor 100 comprises an Instruction Fetch Unit 110 communicatively connected to a Decode Unit 115 and an Instruction Cache Unit (IC) 135. The Decode Unit 115 is communicatively connected to an Execute Unit 120. The Execute Unit 120 is communicatively connected to a Memory Access Unit 125. The Memory Access Unit 125 is communicatively connected to a Register Writeback Unit 130 and a Memory 140. The Register File 105 is communicatively connected to the Instruction Fetch Unit 110, Decode Unit 115, Execute Unit 120, and the Register Writeback Unit 130. In an exemplary embodiment, the Register Writeback Unit 130, however, is only capable of sending signals to the Register File 105, it is incapable of receiving signals from the Register File 105.
The Microprocessor 100 in FIG. 1 receives an instruction sequence, for example instruction n to instruction n+9, as inputs. The Instruction Fetch Unit 110 requests and grabs the instructions from the IC 135. The IC 135 obtains instructions from the main processor memory and stores them locally. The IC 135 serves to reduce the amount of time the Instruction Fetch Unit 110 takes to obtain an instruction. By having the instructions available at the IC 135, the Instruction Fetch Unit 110 does not have to spend additional cycles waiting for an instruction to arrive from the main memory.
When the Instruction Fetch Unit 110 grabs an instruction, it also requests another instruction. Requesting an instruction before it is needed is known as prefetching. By requesting that the IC 135 prefetch an instruction, the Instruction Fetch Unit 110 can further reduce the amount of time it has to wait to receive an instruction. When the Instruction Fetch Unit 110 returns to the IC 135 in order to grab the instruction it previously requested, it will either receive the instruction or have to wait for the IC 135 to obtain the instruction.
Whenever a requested instruction is not immediately available to the Instruction Fetch Unit 110, the IC 135 sends a wait signal to the Instruction Fetch Unit 110. This indicates to the Instruction Fetch Unit 110 that it needs to wait to receive the request and to wait before making any additional prefetch requests.
When an Instruction Fetch Unit 110 receives instruction n from the IC 135, it next requests instruction n+1. At the next clock cycle, if a wait has not been received from the IC 135, instruction n+2 is requested by the Instruction Fetch Unit 110. The Instruction Fetch Unit 110 receives instruction n+1 and the Decode Unit 115 receives instruction n. This process will continue throughout the Microprocessor 100 until instruction n has passed through each unit and a result is written back to the Register File 105.
Although the pipeline process increases the speed in which groups of instructions are processed, it has difficulty handling instructions that are dependent on the results from a preceding status instruction. A status instruction is an instruction that causes a change in the status of the system, such as whether the interrupts are on or off or a change from user mode to system mode. Once a status instruction has changed the status of the process, the Register File 105 will return an incorrect result if queried for a result during the status change.
Results from instructions are written to the Register File 105. Therefore, whenever an instruction requires a result from a previous instruction, it searches the Register File 105 for the result. One problem that occurs is that in some cases the result has not been written to the Register File 105. For example, if at the Execute Unit 120 a new result is computed, it has to propagate through the Memory Access Unit 125 and the Register Writeback Unit 130 before it is written to the Register File 105. A similar problem can occur with a status change of the system. If the status of the system has changed, due to a status instruction, accesses to resources that depend on the current processor status will return incorrect results until the new status has propagated through the processor pipeline.
One method for resolving these problems is data forwarding. Data forwarding, as its name implies, forwards data or results from a first instruction to a second, or dependent, instruction that is waiting for the result. Through data forwarding, the dependent instruction may proceed through the pipeline without errors or delays. Data forwarding allows the status of the system to be forwarded to the dependent instruction. The requesting instruction would then be able to obtain the correct information.
The problem with data forwarding, however, is that it requires additional hardware to implement. This results in a larger chip that consumes additional power. In addition, in many instances the data forwarding would have to be setup along a critical path. That would affect the overall speed of the system.
The present invention is directed to overcoming one or more problems presented above.